PIC18F26K80-I Datasheet, PDF (370/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

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23.8 Use of the Special Event Triggers
A/D conversion can be started by the Special Event
Trigger of any of these modules:
• CCP2 – Requires CCP2M<3:0> bits
(CCP2CON<3:0>) set at ‘1011’^(†)
• ECCP1
• CTMU – Requires the setting of the CTTRIG bit
(CTMUCONH<0>)
• Timer1
To start an A/D conversion:
• The A/D module must be enabled (ADON = 1)
• The appropriate analog input channel selected
• The minimum acquisition period set one of these
ways:
- Timing provided by the user
- Selection made of an appropriate TACQ time
With these conditions met, the trigger sets the
GO/DONE bit and the A/D acquisition starts.
If the A/D module is not enabled (ADON = 0), the
module ignores the Special Event Trigger.
Note:
With an ECCP1 or CCP2 trigger, Timer1
or Timer3 is cleared. The timers reset to
automatically repeat the A/D acquisition
period with minimal software overhead
(moving ADRESH:ADRESL to the desired
location). If the A/D module is not enabled,
the Special Event Trigger is ignored by the
module, but the timer’s counter resets.
23.9 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined, in part, by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used.
After the power-managed mode is entered (either of the
power-managed Run modes), an A/D acquisition or
conversion may be started. Once an acquisition or con-
version is started, the device should continue to be
clocked by the same power-managed mode clock source
until the conversion has been completed. If desired, the
device may be placed into the corresponding
power-managed Idle mode during the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires that the A/D RC
clock be selected. If bits, ACQT<2:0>, are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry into Sleep mode. The
IDLEN and SCS<1:0> bits in the OSCCON register
must have already been cleared prior to starting the
conversion.
DS39977F-page 370
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