PIC18F26K80-I Datasheet, PDF (570/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
FIGURE 31-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SCK
(CKPx = 0)
78
SCK
(CKPx = 1)
SDO
80
MSb
79
bit 6 - - - - - - 1
75, 76
SDI
MSb In
bit 6 - - - - 1
74
73
Note: Refer to Figure 31-3 for load conditions.
79
78
LSb
LSb In
TABLE 31-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
20
— ns
73A TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns
of Byte 2
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
40
— ns
75
TDOR
SDO Data Output Rise Time
—
25 ns
76
TDOF
SDO Data Output Fall Time
—
25 ns
78
TSCR
SCK Output Rise Time (Master mode)
—
25 ns
79
TSCF
SCK Output Fall Time (Master mode)
—
25 ns
80
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
—
50 ns
Conditions
DS39977F-page 570
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