PIC18F26K80-I Datasheet, PDF (295/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
21.3.9
OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full-power mode; in
the case of the Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock can be from the primary clock source, the
secondary clock (SOSC oscillator) or the INTOSC
source. See Section 3.3 “Clock Sources and
Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupt is enabled, it can wake the controller
from Sleep mode, or one of the Idle modes, when the
master completes sending data. If an exit from Sleep or
Idle mode is not desired, MSSP interrupts should be
disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set,
and if enabled, will wake the device.
21.3.10 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
21.3.11 BUS MODE COMPATIBILITY
Table 21-1 shows the compatibility between the
standard SPI modes, and the states of the CKP and
CKE control bits.
TABLE 21-1: SPI BUS MODES
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit which controls when the data
is sampled.
TABLE 21-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
TRISA
TRISA7 TRISA6 TRISA5
—
TRISA3
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3
SSPBUF
MSSP Receive Buffer/Transmit Register
SSPCON1
WCOL SSPOV SSPEN
CKP
SSPM3
SSPSTAT
SMP
CKE
D/A
P
S
ODCON
SSPOD CCP5OD CCP4OD CCP3OD CCP2OD
PMD0
CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD
Legend: Shaded cells are not used by the MSSP module in SPI mode.
TMR0IF
TMR1GIF
TMR1GIE
TMR1GIP
TRISA2
TRISC2
SSPM2
R/W
CCP1OD
UART2MD
INT0IF
TMR2IF
TMR2IE
TMR2IP
TRISA1
TRISC1
SSPM1
UA
U2OD
UART1MD
Bit 0
RBIF
TMR1IF
TMR1IE
TMR1IP
TRISA0
TRISC0
SSPM0
BF
U1OD
SSPMD
 2010-2012 Microchip Technology Inc.
DS39977F-page 295