PIC18F26K80-I Datasheet, PDF (59/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
3.5.2
EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-5:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
Clock from
Ext. System
FOSC/4
OSC1/CLKI
PIC18F66K80
OSC2/CLKO
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-6. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-6:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Clock from
Ext. System
Open
OSC1
PIC18F66K80
(HS Mode)
OSC2
3.5.3 PLL FREQUENCY MULTIPLIER
A Phase Lock Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
3.5.3.1 HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at four times the external
oscillating source to produce frequencies up to
64 MHz.
The PLL is enabled by setting the PLLEN bit
(OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>).
For the HF-INTOSC as primary, the PLL must be
enabled with the PLLEN. This provides a software con-
trol for the PLL, enabling even if PLLCFG is set to ‘1’,
so that the PLL is enabled only when the HF-INTOSC
frequency is within the 4 MHz to16 MHz input range.
This also enables additional flexibility for controlling the
application’s clock speed in software. The PLLEN
should be enabled in HF-INTOSC mode only if the
input frequency is in the range of 4 MHz-16 MHz.
FIGURE 3-7:
PLL BLOCK DIAGRAM
PLLCFG (CONFIG1H<4>)
PLL Enable (OSCTUNE<6>)
OSC2
HS or EC
OSC1 Mode
FIN
FOUT
Phase
Comparator
Loop
Filter
4
VCO
SYSCLK
3.5.3.2 PLL and HF-INTOSC
The PLL is available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 64 MHz.
The operation of INTOSC with the PLL is described in
Section 3.6.2 “INTPLL Modes”. Care should be taken
that the PLL is enabled only if the HF-INTOSC
postscaler is configured for 4 MHz, 8 MHz or 16 MHz.
 2010-2012 Microchip Technology Inc.
DS39977F-page 59