PIC18F26K80-I Datasheet, PDF (259/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
19.3 Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the Timer register pair
value selected in the CCPTMR register. When a match
occurs, the CCPx pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
latch)
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
Figure 19-2 gives the Compare mode block diagram
19.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCPxCON register will force
the corresponding CCPx compare output
latch (depending on device configuration)
to the default low level. This is not the
PORTx data latch.
19.3.2 TIMER1/3 MODE SELECTION
If the CCPx module is using the compare feature in
conjunction with any of the Timer1/3 timers, the timers
must be running in Timer mode or Synchronized
Counter mode. In Asynchronous Counter mode, the
compare operation may not work.
Note: Details of the timer assignments for the
CCPx modules are given in Table 19-2.
19.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCPxIE bit is set.
19.3.4 SPECIAL EVENT TRIGGER
All CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode bits
(CCPxM<3:0> = 1011).
For either CCPx module, the Special Event Trigger
resets the Timer register pair for whichever timer
resource is currently assigned as the module’s time
base. This allows the CCPRx registers to serve as a
programmable Period register for either timer.
 2010-2012 Microchip Technology Inc.
DS39977F-page 259