PIC18F26K80-I Datasheet, PDF (347/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
FIGURE 22-7:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1
Start
bit 7/8 Stop
bit
bit
bit 0
Word 1
RCREGx
Start
bit 7/8 Stop bit
bit
Word 2
RCREGx
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 22-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSPIF TMR1GIF TMR2IF TMR1IF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE TMR1GIE TMR2IE TMR1IE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP TMR1GIP TMR2IP TMR1IP
PIR3
—
—
RC2IF
TX2IF CTMUIF CCP2IF CCP1IF
—
PIE3
—
—
RC2IE
TX2IE CTMUIE CCP2IE CCP1IE
—
IPR3
—
—
RC2IP
TX2IP CTMUIP CCP2IP CCP1IP
—
RCSTA1
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D
RCREG1
EUSART1 Receive Register
TXSTA1
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
BAUDCON1 ABDOVF RCIDL
RXDTP TXCKP BRG16
—
WUE
ABDEN
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte
SPBRG1
EUSART1 Baud Rate Generator Register
RCSTA2
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D
RCREG2
EUSART2 Receive Register
TXSTA2
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
BAUDCON2 ABDOVF RCIDL
RXDTP TXCKP BRG16
—
WUE
ABDEN
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte
SPBRG2
EUSART2 Baud Rate Generator Register Low Byte
PMD0
CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD
ODCON
SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD
U1OD
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
 2010-2012 Microchip Technology Inc.
DS39977F-page 347