PIC18F26K80-I Datasheet, PDF (366/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion can start. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 23.3
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
To do an A/D conversion, follow these steps:
1. Configure the A/D module:
• Configure the required A/D pins as analog pins
(ANCON0 and ANCON1)
• Set the voltage reference (ADCON1)
• Select the A/D positive and negative input
channels (ADCON0 and ADCON1)
• Select the A/D acquisition time (ADCON2)
• Select the A/D conversion clock (ADCON2)
• Turn on the A/D module (ADCON0)
2. Configure the A/D interrupt (if desired):
• Clear the ADIF bit (PIR1<6>)
• Set the ADIE bit (PIE1<6>)
• Set the GIE bit (INTCON<7>)
3. Wait the required acquisition time (if required).
4. Start the conversion:
• Set the GO/DONE bit (ADCON0<1>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL)
and, if required, clear bit, ADIF.
7. For the next conversion, begin with Step 1 or 2,
as required.
The A/D conversion time per bit is defined as TAD.
Before the next acquisition starts, a minimum wait
of 2 TAD is required.
FIGURE 23-5:
ANALOG INPUT MODEL
VDD
RS ^ANx
VT = 0.6V
RIC 1k
Sampling
Switch
SS _RSS
VAIN
CPIN
5 pF
VT = 0.6V
ILEAKAGE
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
RSS
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
various junctions
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
CHOLD = 25 pF
VSS
VDD
1 23 4
Sampling Switch (k)
DS39977F-page 366
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