PIC18F26K80-I Datasheet, PDF (473/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
28.2.1 CONTROL REGISTER
Register 28-15 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT Enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
REGISTER 28-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
U-0
R-x
R/W-0
U-0
R/W-x
REGSLP⁽³⁾
—
ULPLVL SRETEN⁽²⁾
—
ULPEN
bit 7
R/W-x
ULPSINK
R/W-0
SWDTEN⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
REGSLP: Regulator Voltage Sleep Enable bit⁽³⁾
1 = Regulator goes into Low-Power mode when device’s Sleep mode is enabled
0 = Regulator stays in normal mode when device’s Sleep mode is activated
bit 6
Unimplemented: Read as ‘0’
bit 5
ULPLVL: Ultra Low-Power Wake-up Output bit
Not valid unless ULPEN = 1.
1 = Voltage on RA0 pin > ~ 0.5V
0 = Voltage on RA0 pin < ~ 0.5V.
bit 4
SRETEN: Regulator Voltage Sleep Disable bit⁽²⁾
1 = If RETEN (CONFIG1L<0>) = 0 and the regulator is enabled, the device goes into Ultra Low-Power
mode in Sleep
0 = The regulator is on when device’s Sleep mode is enabled and the Low-Power mode is controlled
by REGSLP
bit 3
Unimplemented: Read as ‘0’
bit 2
ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates comparator output
0 = Ultra Low-Power Wake-up module is disabled
bit 1
ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
Not valid unless ULPEN = 1.
1 = Ultra Low-Power Wake-up current sink is enabled
0 = Ultra Low-Power Wake-up current sink is disabled
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit⁽¹⁾
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1:
2:
3:
This bit has no effect if the Configuration bits, WDTEN<1:0>, are enabled.
This bit is available only when RETEN = 0.
This bit is disabled on PIC18LF devices.
TABLE 28-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RCON
IPEN SBOREN
CM
RI
TO
PD
POR
WDTCON
REGSLP
—
ULPLVL SRETEN
—
ULPEN ULPSINK
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Bit 0
BOR
SWDTEN
 2010-2012 Microchip Technology Inc.
DS39977F-page 473