PIC18F26K80-I Datasheet, PDF (285/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
20.4.8
OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2/4
will not increment and the state of the module will not
change. If the ECCP1 pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HF-INTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP1 module without change.
20.4.8.1 Operation with Fail-Safe
Clock Monitor (FSCM)
If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2 register
will be set. The ECCP1 will then be clocked from the
internal oscillator clock source, which may have a
different clock frequency than the primary clock.
20.4.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the ECCP module to reset to a state
compatible with previous, non-enhanced CCP modules
used on other PIC18 and PIC16 devices.
 2010-2012 Microchip Technology Inc.
DS39977F-page 285