PIC18F26K80-I Datasheet, PDF (448/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
Table 27-2 shows the relation between the clock
generated by the PLL and the frequency error from
jitter (measured jitter-induced error of 2%, Gaussian
distribution, within 3 standard deviations), as a
percentage of the nominal clock frequency.
This is clearly smaller than the expected drift of a
crystal oscillator, typically specified at 100 ppm or
0.01%. If we add jitter to oscillator drift, we have a total
frequency drift of 0.0132%. The total oscillator
frequency errors for common clock frequencies and bit
rates, including both drift and jitter, are shown in
Table 27-3.
TABLE 27-2: FREQUENCY ERROR FROM JITTER AT VARIOUS PLL GENERATED CLOCK SPEEDS
PLL
Output
P_jitter
T_jitter
Frequency Error at Various Nominal Bit Times (Bit Rates)
8 s
(125 Kb/s)
4 s
(250 Kb/s)
2 s
(500 Kb/s)
1 s
(1 Mb/s)
40 MHz
24 MHz
16 MHz
0.5 ns
0.83 ns
1.25 ns
1 ns
1.67 ns
2.5 ns
0.00125%
0.00209%
0.00313%
0.00250%
0.00418%
0.00625%
0.005%
0.008%
0.013%
0.01%
0.017%
0.025%
TABLE 27-3: TOTAL FREQUENCY ERROR AT VARIOUS PLL GENERATED CLOCK SPEEDS
(100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER)
Nominal PLL Output
Frequency Error at Various Nominal Bit Times (Bit Rates)
8 s
(125 Kb/s)
4 s
(250 Kb/s)
2 s
(500 Kb/s)
1 s
(1 Mb/s)
40 MHz
24 MHz
16 MHz
0.01125%
0.01209%
0.01313%
0.01250%
0.01418%
0.01625%
0.015%
0.018%
0.023%
0.02%
0.027%
0.035%
DS39977F-page 448
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