PIC18F26K80-I Datasheet, PDF (230/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
16.5.4
TIMER3 GATE SINGLE PULSE
MODE
When Timer3 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer3
Gate Single Pulse mode is first enabled by setting the
T3GSPM bit (T3GCON<4>). Next, the T3GGO/
T3DONE bit (T3GCON<3>) must be set.
The Timer3 will be fully enabled on the next increment-
ing edge. On the next trailing edge of the pulse, the
T3GGO/T3DONE bit will automatically be cleared. No
other gate events will be allowed to increment Timer3
until the T3GGO/T3DONE bit is once again set in
software.
Clearing the T3GSPM bit will also clear the T3GGO/
T3DONE bit. (For timing details, see Figure 16-4.)
Simultaneously enabling the Toggle mode and the
Single Pulse mode will permit both sections to work
together. This allows the cycle times on the Timer3 gate
source to be measured. (For timing details, see
Figure 16-5.)
FIGURE 16-4:
TIMER3 GATE SINGLE PULSE MODE
TMR3GE
T3GPOL
T3GSPM
T3GGO/
T3DONE
T3G_IN
Set by Software
Counting Enabled on
Rising Edge of T3G
Cleared by Hardware on
Falling Edge of T3GVAL
T3CKI
T3GVAL
Timer3
TMR3GIF
N
Cleared by Software
N+1
N+2
Set by Hardware on
Falling Edge of T3GVAL
Cleared by
Software
DS39977F-page 230
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