PIC18F26K80-I Datasheet, PDF (233/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
17.0 TIMER4 MODULES
The Timer4 timer modules have the following features:
• Eight-bit Timer register (TMR4)
• Eight-bit Period register (PR4)
• Readable and writable (all registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR4 match of PR4
The Timer4 modules have a control register shown in
Register 17-1. Timer4 can be shut off by clearing
control bit, TMR4ON (T4CON<2>), to minimize power
consumption. The prescaler and postscaler selection of
Timer4 also are controlled by this register. Figure 17-1
is a simplified block diagram of the Timer4 modules.
17.1 Timer4 Operation
Timer4 can be used as the PWM time base for the
PWM mode of the ECCP modules. The TMR4 registers
are readable and writable, and are cleared on any
device Reset. The input clock (FOSC/4) has a prescale
option of 1:1, 1:4 or 1:16, selected by control bits,
T4CKPS<1:0> (T4CON<1:0>). The match output of
TMR4 goes through a four-bit postscaler (that gives a
1:1 to 1:16 inclusive scaling) to generate a TMR4
interrupt, latched in the flag bit, TMR4IF. Table 17-1
gives each module’s flag bit.
The interrupt can be enabled or disabled by setting or
clearing the Timer4 Interrupt Enable bit (TMR4IE),
shown in Table 17-1.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR4 register
• A write to the T4CON register
• Any device Reset – Power-on Reset (POR),
MCLR Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR)
A TMR4 is not cleared when a T4CON is written.
Note:
The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRS register. For
more details, see Register 20-2 and
Register 19-2.
REGISTER 17-1: T4CON: TIMER4 CONTROL REGISTER
U-0
—
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
R/W-0
TMR4ON
R/W-0
T4CKPS1
R/W-0
T4CKPS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
T4OUTPS<3:0>: Timer4 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
TMR4ON: Timer4 On bit
1 = Timer4 is on
0 = Timer4 is off
T4CKPS<1:0>: Timer4 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
 2010-2012 Microchip Technology Inc.
DS39977F-page 233