PIC18F26K80-I Datasheet, PDF (79/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
5.0 RESET
The PIC18F66K80 family devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during Normal Operation
c) MCLR Reset during Power-Managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Configuration Mismatch (CM) Reset
f) Programmable Brown-out Reset (BOR)
g) RESET Instruction
h) Stack Full Reset
i) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.3.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 28.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
5.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the regis-
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 10.0 “Interrupts”. BOR is covered in
Section 5.4 “Brown-out Reset (BOR)”.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Stack Full/Underflow Reset
Pointer
MCLR
External Reset
MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse
Detect
VDD
Brown-out
Reset
BOREN<1:0>
S
OSC1
OST/PWRT
OST
1024 Cycles
10-Bit Ripple Counter
Chip_Reset
R
Q
32 s
INTOSC⁽¹⁾
PWRT 65.5 ms
11-Bit Ripple Counter
Enable PWRT
Enable OST⁽²⁾
Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 5-2 for time-out situations.
 2010-2012 Microchip Technology Inc.
DS39977F-page 79