PIC18F26K80-I Datasheet, PDF (87/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

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5.7 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on a Power-on Reset and unchanged by all
other Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
CM, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 5-3.
These bits are used in software to determine the nature
of the Reset.
Table 5-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
RCON Register
STKPTR Register
Counter⁽¹⁾ _{SBOREN CM RI TO PD POR BOR STKFUL STKUNF}
Power-on Reset
0000h
1
1 1110 0
0
0
RESET Instruction
0000h
u⁽²⁾
u 0uuu u
u
u
Brown-out Reset
0000h
u⁽²⁾
1 111u 0
u
u
MCLR Reset during
0000h
u⁽²⁾
u u1uu u
u
u
Power-Managed Run modes
MCLR Reset during
0000h
u⁽²⁾
u u10u u
u
u
Power-Managed Idle modes and
Sleep mode
WDT Time-out during Full Power 0000h
u⁽²⁾
u u0uu u
u
u
or Power-Managed Run modes
MCLR Reset during Full-Power 0000h
u⁽²⁾
u uuuu u
u
u
execution
Stack Full Reset (STVREN = 1) 0000h
u⁽²⁾
u uuuu u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u⁽²⁾
u uuuu u
u
1
Stack Underflow Error (not an
0000h
u⁽²⁾
u uuuu u
u
1
actual Reset, STVREN = 0)
WDT Time-out during
PC + 2
u⁽²⁾
u u00u u
u
u
Power-Managed Idle or Sleep
modes
Interrupt Exit from
Power-Managed modes
PC + 2
u⁽²⁾
u uu0u u
u
u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0>, Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.
 2010-2012 Microchip Technology Inc.
DS39977F-page 87