PIC18F26K80-I Datasheet, PDF (608/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
Error States....................................................... 452
Form.................................................................. 452
Stuff Bit ............................................................. 452
Error Modes State (diagram) .................................... 453
Error Recognition Mode ............................................ 439
Filter-Mask Truth (table)............................................ 444
Functional Modes...................................................... 439
Mode 0 (Legacy Mode) ..................................... 439
Mode 1 (Enhanced Legacy Mode).................... 439
Mode 2 (Enhanced FIFO Mode) ....................... 440
Information Processing Time (IPT) ........................... 449
Lengthening a Bit Period........................................... 450
Listen Only Mode ...................................................... 439
Loopback Mode ........................................................ 439
Message Acceptance Filters and Masks .......... 421, 444
Message Acceptance Mask and Filter Operation ..... 445
Message Reception .................................................. 443
Enhanced FIFO Mode....................................... 444
Priority............................................................... 443
Time-Stamping.................................................. 444
Normal Mode ............................................................ 438
Oscillator Tolerance .................................................. 451
Overview ................................................................... 391
Phase Buffer Segments ............................................ 449
Programmable TX/RX and Auto-RTR Buffers .......... 413
Programming Time Segments .................................. 451
Propagation Segment ............................................... 449
Sample Point............................................................. 449
Shortening a Bit Period ............................................. 451
Synchronization ........................................................ 450
Hard .................................................................. 450
Resynchronization ............................................ 450
Rules................................................................. 450
Synchronization Segment ......................................... 449
Time Quanta ............................................................. 449
Values for ICODE (table) .......................................... 454
Effect on Standard PIC18 Instructions .............................. 530
Effects of Power-Managed Modes on Various Clock Sources
63
Electrical Characteristics................................................... 537
Enhanced Capture/Compare/PWM (ECCP) ..................... 265
Capture Mode. See Capture.
Compare Mode. See Compare.
ECCP Mode and Timer Resources........................... 268
Enhanced PWM Mode .............................................. 271
Auto-Restart...................................................... 280
Auto-Shutdown ................................................. 278
Direction Change in Full-Bridge Output Mode .. 277
Full-Bridge Application ...................................... 275
Full-Bridge Mode............................................... 275
Half-Bridge Application ..................................... 274
Half-Bridge Application Examples..................... 281
Half-Bridge Mode .............................................. 274
Output Relationships (Active-High and Active-Low)
272
Output Relationships Diagram .......................... 273
Programmable Dead-Band Delay ..................... 281
Shoot-Through Current ..................................... 281
Start-up Considerations .................................... 278
Outputs and Configuration ........................................ 268
Enhanced Capture/Compare/PWM (ECCP) and Timer1/2/3/4
Associated Registers ................................................ 286
Enhanced Universal Synchronous Asynchronous Receiver
Transmitter (EUSART). See EUSART.
Equations
16 x 16 Signed Multiplication Algorithm.................... 146
16 x 16 Unsigned Multiplication Algorithm................ 146
16MHz Clock from 4x PLL Jitter ............................... 447
A/D Acquisition Time ................................................ 367
A/D Minimum Charging Time.................................... 367
Calculating the Minimum Required Acquisition Time 367
Jitter and Total Frequency Error ............................... 447
Resultant Frequency Error........................................ 447
Errata .................................................................................... 9
Error Recognition Mode.................................................... 438
EUSART
Asynchronous Mode ................................................. 343
12-Bit Break Transmit and Receive.................. 350
Associated Registers, Receive......................... 347
Associated Registers, Transmit........................ 345
Auto-Wake-up on Sync Break .......................... 348
Receiver ........................................................... 346
Setting up 9-Bit Mode with Address Detect ...... 346
Transmitter ....................................................... 343
Baud Rate Generator
Operation in Power-Managed Mode................. 337
Baud Rate Generator (BRG) .................................... 337
Associated Registers........................................ 338
Auto-Baud Rate Detect..................................... 341
Baud Rate Error, Calculating............................ 338
Baud Rates, Asynchronous Modes .................. 339
High Baud Rate Select (BRGH Bit) .................. 337
Sampling........................................................... 337
Synchronous Master Mode....................................... 351
Associated Registers, Receive......................... 354
Associated Registers, Transmit........................ 352
Reception ......................................................... 353
Transmission .................................................... 351
Synchronous Slave Mode......................................... 355
Associated Registers, Receive......................... 356
Associated Registers, Transmit........................ 355
Reception ......................................................... 356
Transmission .................................................... 355
Extended Instruction Set
ADDFSR ................................................................... 526
ADDULNK................................................................. 526
CALLW ..................................................................... 527
MOVSF ..................................................................... 527
MOVSS..................................................................... 528
PUSHL...................................................................... 528
SUBFSR ................................................................... 529
SUBULNK................................................................. 529
External Oscillator Modes
Clock Input (EC Modes).............................................. 59
HS............................................................................... 58
F
Fail-Safe Clock Monitor ............................................ 457, 477
Exiting Operation ...................................................... 477
Interrupts in Power-Managed Modes........................ 478
POR or Wake from Sleep ......................................... 478
WDT During Oscillator Failure .................................. 477
Fail-Safe Clock Monitor (FSCM)....................................... 457
Fast Register Stack .......................................................... 105
Firmware Instructions ....................................................... 483
Flash Program Memory .................................................... 129
Associated Registers ................................................ 137
Control Registers ...................................................... 130
EECON1 and EECON2 .................................... 130
TABLAT (Table Latch) Register ....................... 132
DS39977F-page 608
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