PIC18F26K80-I Datasheet, PDF (328/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
FIGURE 21-29:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
SDA
TBRG
TBRG
SCL
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SEN
BCLIF
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
S
‘0’
SSPIF ^{‘0’}
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
Interrupt cleared
in software
‘0’
‘0’
FIGURE 21-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SDA = 0, SCL = 1
Set S
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SSPIF
SCL
SEN
BCLIF
S
SCL pulled low after BRG
time-out
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
S
SSPIF
SDA = 0, SCL = 1,
set SSPIF
Interrupts cleared
in software
DS39977F-page 328
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