PIC18F26K80-I Datasheet, PDF (187/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
11.6 PORTE, TRISE and
LATE Registers
PORTE is a seven-bit-wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISE and LATE.
Note: PORTE is unavailable on 28-pin devices.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note: These pins are configured as digital inputs
on any device Reset.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PADCFG1<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
PORTE is also multiplexed with the Parallel Slave Port
address lines. RE1 and RE0 are multiplexed with the
Parallel Slave Port (PSP) control signals, WR and RD.
EXAMPLE 11-5: INITIALIZING PORTE
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
03h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
TABLE 11-9: PORTE FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O I/O Type
Description
RE0/AN5/RD
RE0
0
O
DIG LATE<0> data output.
1
I
ST PORTE<0> data input.
AN5
1
I
ANA A/D Input Channel 5. Default input configuration on POR; does not
affect digital output.
RD
x
O
DIG Parallel Slave Port read strobe pin.
x
I
ST Parallel Slave Port read pin.
RE1/AN6/
RE1
0
O
DIG LATE<1> data output.
C1OUT/WR
1
I
ST PORTE<1> data input.
AN6
1
I
ANA A/D Input Channel 5. Default input configuration on POR; does not
affect digital output.
C1OUT
0
O
DIG Comparator 1 output; takes priority over port data.
WR
x
O
DIG Parallel Slave Port write strobe pin.
RE2/AN7/
C2OUT/CS
x
I
ST Parallel Slave Port write pin.
RE2
0
O
DIG LATE<2> data output.
1
I
ST PORTE<2> data input.
AN7
1
I
ANA A/D Input Channel 7. Default input configuration on POR; does not
affect digital output.
C2OUT
0
O
DIG Comparator 2 output; takes priority over port data.
RE3
RE4/CANRX
CS
RE3
RE4⁽¹⁾
x
I
ST Parallel Slave Port chip select.
1
I
ST PORT<3> data input.
0
O
DIG LATE<4> data output.
Legend:
Note 1:
2:
1
I
ST PORTE<4> data input.
CANRX^(1,2)
1
I
ST CAN bus RX.
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
These bits are unavailable for 40 and 44-pin devices (PIC18F4XK0).
This is the alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX
Configuration bit is cleared.
 2010-2012 Microchip Technology Inc.
DS39977F-page 187