PIC18F26K80-I Datasheet, PDF (228/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
16.5 Timer3 Gates
Timer3 can be configured to count freely or the count
can be enabled and disabled using the Timer3 gate
circuitry. This is also referred to as the Timer3 gate
count enable.
The Timer3 gate can also be driven by multiple
selectable sources.
16.5.1 TIMER3 GATE COUNT ENABLE
The Timer3 Gate Enable mode is enabled by setting
the TMR3GE bit (TxGCON<7>). The polarity of the
Timer3 Gate Enable mode is configured using the
T3GPOL bit (T3GCON<6>).
When Timer3 Gate Enable mode is enabled, Timer3 will
increment on the rising edge of the Timer3 clock source.
When Timer3 Gate Enable mode is disabled, no incre-
menting will occur and Timer3 will hold the current count.
See Figure 16-2 for timing details.
TABLE 16-1: TIMER3 GATE ENABLE
SELECTIONS
T3CLK^(†)
T3GPOL
(T3GCON<6>)
T3G Pin
Timer3
Operation

0
0 Counts

0
1 Holds Count

1
0 Holds Count

1
1 Counts
† The clock on which TMR3 is running. For more
information, see T3CLK in Figure 16-1.
FIGURE 16-2:
TMR3GE
TIMER3 GATE COUNT ENABLE MODE
T3GPOL
T3G_IN
T3CKI
T3GVAL
Timer3
N
N+1
N+2
N+3
N+4
DS39977F-page 228
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