PIC18F26K80-I Datasheet, PDF (250/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

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18.8 Creating a Delay with the CTMU
Module
A unique feature on board the CTMU module is its ability
to generate system clock independent output pulses
based on either an external voltage or an external
capacitor value. When using an external voltage, this is
accomplished using the CTDIN input pin as a trigger for
the pulse delay. When using an external capacitor
value, this is accomplished using the internal compara-
tor voltage reference module and Comparator 2 input
pin.The pulse is output onto the CTPLS pin. To enable
this mode, set the TGEN bit.
See Figure 18-5 for an example circuit. When
CTMUDS (PADCFG1<0>) is cleared, the pulse delay is
determined by the output of Comparator 2, and when it
is set, the pulse delay is determined by the input of
CTDIN. CDELAY is chosen by the user to determine the
output pulse width on CTPLS. The pulse width is calcu-
lated by T = (CDELAY/I)*V, where I is known from the
current source measurement step (Section 18.4.1
“Current Source Calibration”) and V is the internal
reference voltage (CVREF).
An example use of the external capacitor feature is
interfacing with variable capacitive-based sensors,
such as a humidity sensor. As the humidity varies, the
pulse-width output on CTPLS will vary. An example use
of the CTDIN feature is interfacing with a digital sensor.
The CTPLS output pin can be connected to an input
capture pin and the varying pulse width measured to
determine the sensor’s output in the application.
To use this feature:
1. If CTMUDS is cleared, initialize Comparator 2.
2. If CTMUDS is cleared, initialize the comparator
voltage reference.
3. Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
4. Set EDG1STAT.
When CTMUDS is cleared, as soon as CDELAY
charges to the value of the voltage reference trip point,
an output pulse is generated on CTPLS. When
CTMUDS is set, as soon as CTDIN is set, an output
pulse is generated on CTPLS.
FIGURE 18-5:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY
GENERATION
CTED1
CTMUI
PIC18F66K80
CTMU
EDG1
Current Source
Comparator
C2
CTPLS
CTMUDS
CTDIN
CDELAY
CVREF
C1
External Reference
External Comparator
DS39977F-page 250
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