PIC18F26K80-I Datasheet, PDF (169/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
10.9 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack.
If a fast return from interrupt is not used (see
Section 6.3 “Data Memory Organization”), the user
may need to save the WREG, STATUS and BSR regis-
ters on entry to the Interrupt Service Routine (ISR).
Depending on the user’s application, other registers
also may need to be saved.
Example 10-1 saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP
MOVFF STATUS, STATUS_TEMP
MOVFF BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR
MOVF W_TEMP, W
MOVFF STATUS_TEMP, STATUS
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
INTCON2
INTCON3
PIR1
PIR2
PIR3
PIR4
PIR5
PIE1
PIE2
PIE3
PIE4
PIE5
IPR1
IPR2
IPR3
IPR4
IPR5
RBPU
INT2IP
PSPIP
OSCFIF
—
TMR4IF
IRXIF
PSPIE
OSCFIE
—
TMR4IE
IRXIE
PSPIP
OSCFIP
—
TMR4IP
IRXIP
INTEDG0
INT1IP
ADIF
—
—
EEIF
WAKIF
ADIE
—
—
EEIE
WAKIE
ADIP
—
—
EEIP
WAKIP
INTEDG1
INT3IE
RC1IF
—
RC2IF
CMP2IF
ERRIF
RC1IE
—
RC2IE
CCP2IE
ERRIE
RC1IP
—
RC2IP
CMP2IP
ERRIP
INTEDG2
INT2IE
TX1IF
—
TX2IF
CMP1IF
TXB2IF
TX1IE
—
TX2IE
CMP1IE
TXB2IE
TX1IP
—
TX2IP
CMP1IP
TXB2IP
RCON
IPEN
SBOREN
CM
RI
Legend: Shaded cells are not used by the interrupts.
Bit 3
RBIE
INTEDG3
INT1IE
SSPIF
BCLIF
CTMUIF
—
TXB1IF
SSPIE
BCLIE
CTMUIE
—
TXB1IE
SSPIP
BCLIP
CTMUIP
—
TXB1IP
TO
Bit 2
TMR0IF
TMR0IP
INT3IF
TMR1GIF
HLVDIF
CCP2IF
CCP5IF
TXB0IF
TMR1GIE
HLVDIE
CCP2IE
CCP5IE
TXB0IE
TMR1GIP
HLVDIP
CCP2IP
CCP5IP
TXB0IP
PD
Bit 1
INT0IF
INT3IP
INT2IF
TMR2IF
TMR3IF
CCP1IF
CCP4IF
RXB1IF
TMR2IE
TMR3IE
CCP1IE
CCP4IE
RXB1IE
TMR2IP
TMR3IP
CCP1IP
CCP4IP
RXB1IP
POR
Bit 0
RBIF
RBIP
INT1IF
TMR1IF
TMR3GIF
—
CCP3IF
RXB0IF
TMR1IE
TMR3GIE
—
CCP3IE
RXB0IE
TMR1IP
TMR3GIP
—
CCP3IP
RXB0IP
BOR
 2010-2012 Microchip Technology Inc.
DS39977F-page 169