PIC18F26K80-I Datasheet, PDF (290/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
21.3.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP module consists of a Transmit/Receive Shift
register (SSPSR) and a Buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision Detect bit,
WCOL (SSPCON1<7>), will be set. User software
must clear the WCOL bit so that it can be determined if
the following write(s) to the SSPBUF register
completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur. Example 21-1
shows the loading of the SSPBUF (SSPSR) for data
transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various status conditions.
21.3.3 OPEN-DRAIN OUTPUT OPTION
The drivers for the SDO output and SCK clock pins can
be optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
to a higher level through an external pull-up resistor,
and allows the output to communicate with external cir-
cuits without the need for additional level shifters. For
more information, see Section 11.1.3 “Open-Drain
Outputs”.
The open-drain output option is controlled by the
SSPOD bit (ODCON<7>). Setting the SSPOD bit
configures the SDO and SCK pins for open-drain
operation.
EXAMPLE 21-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP
BTFSS
BRA
MOVF
SSPSTAT, BF
LOOP
SSPBUF, W
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS39977F-page 290
 2010-2012 Microchip Technology Inc.