PIC18F26K80-I Datasheet, PDF (226/622 Pages) Microchip Technology – 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

PIC18F66K80 FAMILY
16.2 Timer3 Operation
Timer3 can operate in these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
The operating mode is determined by the clock select
bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits
are cleared (= 00), Timer3 increments on every internal
instruction cycle (FOSC/4). When TMR3CSx = 01, the
Timer3 clock source is the system clock (FOSC), and
when it is ‘10’, Timer3 works as a counter from the
external clock from the T3CKI pin (on the rising edge
after the first falling edge) or the SOSC oscillator.
FIGURE 16-1:
TIMER3 BLOCK DIAGRAM
T3GSS<1:0>
T3G
00
T3GSPM
From TMR4
Match PR4
01
From Comparator 1
Output
10
From Comparator 2
Output
11
T3GPOL
T3G_IN
TMR3ON
T3GTM
DQ
CK ^Q
R
Set Flag bit,
TMR3IF, on
Overflow
TMR3⁽²⁾
TMR3H
TMR3L
0
Single Pulse
1
Acq. Control
T3GGO/T3DONE
0
T3GVAL
DQ
1
Q1 EN
Interrupt
det
TMR3ON
TMR3GE
Data Bus
RD
T3GCON
Set
TMR3GIF
EN
T3CLK
0
QD
Synchronized
Clock Input
1
SOSCO/SCLKI
OUT⁽⁴⁾
TMR3CS<1:0>
T3SYNC
SOSCI
T1CON.SOSCEN
T3CON.SOSCEN
SOSCGO
SCS<1:0> = 01
T3CKI
SOSC
EN
(1)
Prescaler
Synchronize⁽³⁾
1
1, 2, 4, 8
det
10
0
FOSC
2
T3CKPS<1:0>
Internal ⁰¹
Clock
FOSC/4
Internal ⁰⁰
FOSC/2
Internal
Clock
Sleep Input
Clock
Note 1:
2:
3:
4:
ST Buffer is high-speed type when using T3CKI.
Timer3 registers increment on rising edge.
Synchronization does not operate while in Sleep.
The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits.
DS39977F-page 226
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