MC68HC11P2 Datasheet, PDF (93/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
SCI registers
The OR is cleared when the SCSR is read (with OR set), followed by a
read of the SCI data registers.
The noise flag (NF) bit is set if there is noise on any of the received bits,
including the start and stop bits. The NF bit is not set until the RDRF flag
is set. The NF bit is cleared when the SCSR is read (with FE equal to
one) followed by a read of the SCI data registers.
When no stop bit is detected in the received data character, the framing
error (FE) bit is set. FE is set at the same time as the RDRF. If the byte
received causes both framing and overrun errors, the processor only
recognizes the overrun error. The framing error flag inhibits further
transfer of data into the SCI data registers until it is cleared. The FE bit
is cleared when the SCSR is read (with FE equal to one) followed by a
read of the SCI data registers.
The parity error flag (PF) is set if received data has incorrect parity. The
flag is cleared by a read of SCSR1 with PE set, followed by a read of
SCDR.
5.8 SCI registers
There are eight addressable registers in the SCI. SCBDH, SCBDL,
SCCR1, and SCCR2 are control registers. The contents of these
registers control functions and indicate conditions within the SCI. The
status registers SCSR1 and SCSR2 contain bits that indicate certain
conditions within the SCI. SCDRH and SCDRL are SCI data registers.
These double buffered registers are used for the transmission and
reception of data, and are used to form the 9-bit data word for the SCI.
If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be
accessed. Note that if 9-bit data format is used, the upper register should
be written first to ensure that it is transferred to the transmitter shift
register with the lower register.
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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Technical Data