MC68HC11P2 Datasheet, PDF (225/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Instruction set
Table 11-2. Instruction set (Sheet 3 of 8)
Mnemonic
BRCLR(opr)
(msk)
(rel)
BRN (rel)
BRSET(opr)
(msk)
(rel)
BSET (opr)
(msk)
BSR (rel)
BVC (rel)
BVS (rel)
CBA
CLC
CLI
CLR (opr)
Operation
Branch if bit(s) clear
Branch never
Branch if bit(s) set
Set bit(s)
Branch to subroutine
Branch if overflow clear
Branch if overflow set
Compare A with B
Clear carry bit
Clear interrupt mask
Clear memory byte
CLRA
CLRB
CLV
CMPA (opr)
Clear accumulator A
Clear accumulator B
Clear overflow flag
Compare A with memory
CMPB (opr) Compare B with memory
COM (opr) Ones complement memory byte
COMA
Ones complement A
COMB
Ones complement B
CPD (opr) Compare D with memory (16-bit)
Description
M • mm = 0 ?
1=0?
M • mm = 0 ?
M + mm ⇒ M
see Figure 11-2
V=0?
V=1?
A–B
0⇒C
0⇒I
0⇒M
0⇒A
0⇒B
0⇒V
A–M
B–M
$FF – M ⇒ M
$FF – A ⇒ A
$FF – B ⇒ B
D – (M:M+1)
Addressing
mode
DIR
IND, X
IND, Y
REL
DIR
IND, X
IND, Y
DIR
IND, X
IND, Y
REL
REL
REL
INH
INH
INH
DIR
IND, X
IND, Y
A INH
B INH
INH
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
EXT
IND, X
IND, Y
A INH
B INH
IMM
DIR
EXT
IND, X
IND, Y
Opcode
13
1F
18 1F
21
12
1E
18 1E
14
1C
18 1C
8D
28
29
11
0C
0E
7F
6F
18 6F
4F
5F
0A
81
91
B1
A1
18 A1
C1
D1
F1
E1
18 E1
73
63
18 63
43
53
1A 83
1A 93
1A B3
1A A3
CDA3
Instruction
Operand
dd mm rr
ff mm rr
ff mm rr
rr
dd mm rr
ff mm rr
ff mm rr
dd mm
ff mm
ff mm
rr
rr
rr
—
—
—
hh ll
ff
ff
—
—
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
—
—
jj kk
dd
hh ll
ff
ff
Cycles
6
7
8
3
6
7
8
6
7
8
6
3
3
2
2
2
6
6
7
2
2
2
2
3
4
4
5
2
3
4
4
5
6
6
7
2
2
5
6
7
7
7
Condition codes
SXH I NZVC
————————
————————
————————
————∅∅ 0 —
————————
————————
————————
————∅∅∅∅
——————— 0
——— 0 ————
———— 0 1 0 0
———— 0 1 0 0
———— 0 1 0 0
—————— 0 —
————∅∅∅∅
————∅∅∅∅
————∅∅ 0 1
————∅∅ 0 1
————∅∅ 0 1
————∅∅∅∅
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
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Technical Data