MC68HC11P2 Datasheet, PDF (227/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Instruction set
Table 11-2. Instruction set (Sheet 5 of 8)
Mnemonic
LDAA (opr)
Operation
Load accumulator A
LDAB (opr)
Load accumulator B
LDD (opr) Load double accumulator D
LDS (opr)
Load stack pointer
LDX (opr)
Load index register X
LDY (opr)
Load index register Y
LSL (opr)
LSLA
LSLB
LSLD
LSR (opr)
LSRA
LSRB
LSRD
Logical shift left
Logical shift left A
Logical shift left B
Logical shift left D
Logical shift right
Logical shift right A
Logical shift right B
Logical shift right D
Description
M⇒A
M⇒B
M ⇒ A; M+1 ⇒ B
M:M+1 ⇒ SP
M:M+1 ⇒ IX
M:M+1 ⇒ IY
C
b7
0
b0
C
b15
0
b0
0
b7
C
b0
0
b15
C
b0
Addressing
mode
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
EXT
IND, X
IND, Y
A INH
B INH
INH
Opcode
86
96
B6
A6
18 A6
C6
D6
F6
E6
18 E6
CC
DC
FC
EC
18 EC
8E
9E
BE
AE
18 AE
CE
DE
FE
EE
CDEE
18 CE
18 DE
18 FE
1A EE
18 EE
78
68
18 68
48
58
05
Instruction
Operand
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
hh ll
ff
ff
—
—
—
Cycles
2
3
4
4
5
2
3
4
4
5
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6
4
5
6
6
6
6
6
7
2
2
3
Condition codes
SXH I NZVC
————∅∅ 0 —
————∅∅ 0 —
————∅∅ 0 —
————∅∅ 0 —
————∅∅ 0 —
————∅∅ 0 —
————∅∅∅∅
————∅∅∅∅
————∅∅∅∅
————∅∅∅∅
EXT
IND, X
IND, Y
A INH
B INH
INH
74 hh ll
64 ff
18 64 ff
44 —
54 —
04 —
6 ———— 0 ∅∅∅
6
7
2 ———— 0 ∅∅∅
2 ———— 0 ∅∅∅
3 ———— 0 ∅∅∅
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
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Technical Data