MC68HC11P2 Datasheet, PDF (215/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Registers
• The decimal adjust accumulator A (DAA) instruction is used after
binary-coded decimal (BCD) arithmetic operations, but there is no
equivalent BCD instruction to adjust accumulator B.
• The add, subtract, and compare instructions associated with both
A and B (ABA, SBA, and CBA) only operate in one direction,
making it important to plan ahead to ensure the correct operand is
in the correct accumulator.
11.3.2 Index register X (IX)
The IX register provides a 16-bit indexing value that can be added to the
8-bit offset provided in an instruction to create an effective address. The
IX register can also be used as a counter or as a temporary storage
register.
11.3.3 Index register Y (IY)
The 16-bit IY register performs an indexed mode function similar to that
of the IX register. However, most instructions using the IY register
require an extra byte of machine code and an extra cycle of execution
time because of the way the opcode map is implemented. Refer to
Opcodes and operands for further information.
11.3.4 Stack pointer (SP)
The M68HC11 CPU has an automatic program stack. This stack can be
located anywhere in the address space and can be any size up to the
amount of memory available in the system. Normally the SP is initialized
by one of the first instructions in an application program. The stack is
configured as a data structure that grows downward from high memory
to low memory. Each time a new byte is pushed onto the stack, the SP
is decremented. Each time a byte is pulled from the stack, the SP is
incremented. At any given time, the SP holds the 16-bit address of the
next free location in the stack. Figure 11-2 is a summary of SP
operations.
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Technical Data