MC68HC11P2 Datasheet, PDF (223/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Instruction set
11.7 Instruction set
Refer to Table 11-2, which shows all the M68HC11 instructions in all
possible addressing modes. For each instruction, the table shows the
operand construction, the number of machine code bytes, and execution
time in CPU E clock cycles.
Mnemonic
ABA
ABX
ABY
ADCA (opr)
ADCB (opr)
ADDA (opr)
ADDB (opr)
ADDD (opr)
ANDA (opr)
Table 11-2. Instruction set (Sheet 1 of 8)
Operation
Add accumulators
Add B to X
Add B to Y
Add with carry to A
Add with carry to B
Add memory to A
Add memory to B
Add 16-bit to D
AND A with memory
Description
A+B⇒A
IX + (00:B) ⇒ IX
IY + (00:B) ⇒ IY
A+M+C⇒A
B+M+C⇒B
A+M⇒A
B+M⇒B
D + (M:M+1) ⇒ D
A•M⇒A
Addressing
mode
INH
INH
INH
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
A IMM
A DIR
A EXT
A IND, X
A IND, Y
B IMM
B DIR
B EXT
B IND, X
B IND, Y
IMM
DIR
EXT
IND, X
IND, Y
A IMM
A DIR
A EXT
A IND, X
A IND, Y
Opcode
1B
3A
18 3A
89
99
B9
A9
18 A9
C9
D9
F9
E9
18 E9
8B
9B
BB
AB
18 AB
CB
DB
FB
EB
18 EB
C3
D3
F3
E3
18 E3
84
94
B4
A4
18 A4
Instruction
Operand
—
—
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
Cycles
2
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
3
4
4
5
Condition codes
SXH I NZVC
——∅—∅∅∅∅
————————
————————
——∅—∅∅∅∅
——∅—∅∅∅∅
——∅—∅∅∅∅
——∅—∅∅∅∅
————∅∅∅∅
————∅∅ 0 —
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
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Go to: www.freescale.com
Technical Data