MC68HC11P2 Datasheet, PDF (242/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Electrical Specifications
12.7.3 Serial peripheral interface timing
(V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H)
Num
Characteristic ⁽¹⁾
2.0 MHz
3.0 MHz
Symbol
Min. Max. Min. Max.
Operating frequencyMaster
Slave
f_OP(M)
0
0.5
0
0.5
f_OP(S)
0 2.0 0 3.0
1
Cycle timeMaster
Slave
t_{CYC(M) 2.0 — 2.0 —}
t_CYC(S) 500 — 333 —
2 ^{Enable lead time (2) Master}
Slave
t_{LEAD(M) —}
—
—
—
t_LEAD(S) 250 — 240 —
3 ^{Enable lag time (2) Master}
Slave
t_{LAG(M) —}
—
—
—
t_LAG(S) 250 — 240 —
4
Clock (SCK) high timeMaster
Slave
t_{W(SCKH) 340 — 227 —}
M
t_W(SCKH)S
190
—
127
—
5
Clock (SCK) low timeMaster
Slave
t_{W(SCKL)M 340 — 227 —}
t_W(SCKL)S 190 — 127 —
6
Input data set-up timeMaster
Slave
t_{SU(M) 100 — 100 —}
t_SU(S) 100 — 100 —
7
Input data hold timeMaster
Slave
t_H(M)
t_H(S)
100 — 100 —
100 — 100 —
8
Access time (from high-z to data active)
Slave
t_A
0 120 0 120
9 Disable time (hold time to high-z state)Slave t_DIS
— 240 — 167
10 _{Data valid (after enable edge)} ⁽³⁾
t_V(S)
— 240 — 167
11 Output data hold time (after enable edge)
t_HO
0—0—
Rise time ⁽³⁾
12 _{SPI outputs (SCK, MOSI and MISO)}
SPI inputs (SCK, MOSI, MISO and SS)
t_RM
— 100 — 100
t_RS
— 2.0 — 2.0
Fall time ⁽³⁾
13 _{SPI outputs (SCK, MOSI and MISO)}
SPI inputs (SCK, MOSI, MISO and SS)
t_FM
— 100 — 100
t_FS
— 2.0 — 2.0
1. All timing is given with respect to 20% and 70% of V_DD, unless otherwise noted.
2. Signal production depends on software.
3. Assumes 200pF load on all SPI pins.
4.0 MHz
Min. Max.
0 0.5
0 4.0
2.0 —
250 —
——
200 —
——
200 —
130 —
85 —
130 —
85 —
100 —
100 —
100 —
100 —
0 120
— 125
— 125
0—
— 100
— 2.0
— 100
— 2.0
Unit
f_OP
MHz
t_CYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
Technical Data
Electrical Specifications
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Go to: www.freescale.com
MC68HC11P2 — Rev 1.0