MC68HC11P2 Datasheet, PDF (237/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Electrical Specifications
Control timing
12.7 Control timing
(V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H)
Characteristic ⁽¹⁾
Symbol
2.0 MHz
3.0 MHz
4.0 MHz
Min. Max. Min. Max. Min. Max.
Frequency of operation
f_OP
0
2.0
0
3.0
0
4.0
E clock period
t_CYC
500 — 333 — 250 —
Crystal frequency
f_XTAL
— 8.0 — 12.0 — 16.0
External oscillator frequency
4f_OP
0
8.0
0 12.0 0 16.0
Processor control set-up time (t_PCSU = t_CYC/4 + 50ns)
t_PCSU
175 — 133 — 112 —
Reset input pulse width ⁽²⁾
PPWW_{RRSSTTLL((34))}
8
1
—
—
8
1
—
—
8
1
—
—
Mode programming set-up time
t_MPS
2
—
2
—
2
—
Mode programming hold time
t_MPH
10
—
10
—
10
—
Interrupt pulse width (IRQ edge sensitive mode) PW_IRQ t_CYC +20 — t_CYC +20 — t_CYC +20 —
Timer pulse width
(Input capture and pulse accumulator inputs)
PW_TIM t_CYC +20 — t_CYC +20 — t_CYC +20 —
WAIT recovery start-up time
t_WRS
—
4
—
4
—
4
Clock monitor reset
f_CMON
10 200 10 200 10 200
PLL crystal frequency
f_XTAL
— 2.0 — 2.0 — 2.0
PLL stabilization time
t_PLLS
— TBD — TBD — TBD
Unit
MHz
ns
MHz
MHz
ns
t_CYC
t_CYC
ns
ns
ns
t_CYC
kHz
MHz
ms
1. All timing is given with respect to 20% and 70% of V_DD, unless otherwise noted.
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin and samples the pin level two cycles later to determine the source of the interrupt. (See Resets and Inter-
rupts.)
3. To guarantee an external reset vector.
4. This is the minimum input time; it can be pre-empted by an internal reset.
PA[3:0]⁽¹⁾
PA[3:0]⁽²⁾
PW_TIM
PA7^{(1), (3)}
PA7^{(2), (3)}
Notes
(1) Rising edge sensitive input.
(2) Falling edge sensitive input.
(3) Maximum pulse accumulator clocking rate is E clock frequency divided by two (E/2).
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Technical Data