MC68HC11P2 Datasheet, PDF (153/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timing System
Output compare
These bits are used to select the prescaler divide-by ratio. In normal
modes, PR[1:0] can only be written once, and the write must be within
64 cycles after reset. See Table 8-1 for specific timing values.
8.5.10 TFLG2 — Timer interrupt flag register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer interrupt flag 2 (TFLG2) $0025 TOF RTIF PAOVF PAIF 0
0
0
0 0000 0000
Bits in this register indicate when certain timer system events have
occurred. Coupled with the four high-order bits of TMSK2, the bits of
TFLG2 allow the timer subsystem to operate in either a polled or
interrupt driven system. Clear flags by writing a one to the corresponding
bit position(s).
NOTE: Bits in TFLG2 correspond bit for bit with flag bits in TMSK2. Ones in
TMSK2 enable the corresponding interrupt sources.
TOF — Timer overflow interrupt flag
1 = TCNT has overflowed from $FFFF to $0000.
0 = No timer overflow has occurred.
RTIF — Real time (periodic) interrupt flag (refer to Real-time interrupt)
PAOVF — Pulse accumulator overflow interrupt flag (refer to Pulse
accumulator)
PAIF — Pulse accumulator input edge interrupt flag (refer to Pulse
accumulator.)
Bits [3:0] — Not implemented; always read zero
MC68HC11P2 — Rev 1.0
Timing System
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Technical Data