MC68HC11P2 Datasheet, PDF (112/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Motorola Interconnect Bus (MI BUS)
6.4 The push field
The push field consists of a start bit, a push synchronization bit, a push
data field and a push address field. The start consists of three time slots
having the dominant logical state ‘0’. The start marks the beginning of
the message frame by violation of the rule of the Manchester code. The
push synchronization bit consists of a biphase coded ‘0’. Biphase coding
will be discussed later. The push data field consists of five bits of biphase
coded data. The push address consists of three bits of biphase coded
data. Data and address are written to the lower byte of the SCI data
register (S2DRL). The push data occupies the lower five bits and the
push address occupies the upper three bits of the register.
6.5 The pull field
The pull field consists of a pull synchronization bit, a pull data field and
an end of frame. The pull synchronization bit is a biphase coded ‘1’ and
is initiated by the MCU during the time slot after the last address bit of
the push field. The pull data field consists of an NRZ coded transmission,
each bit taking one time slot. Once shifted in, the pull data is stored in
the lower byte of the SCI data register (S2DRL). The end-of-frame field
is a square wave signal having a typical frequency of 20kHz ± 1%
tolerance (i.e. the bit rate of the push field) when the data sent to the
selected device is valid.
Technical Data
Motorola Interconnect Bus (MI BUS)
For More Information On This Product,
Go to: www.freescale.com
MC68HC11P2 — Rev 1.0