MC68HC11P2 Datasheet, PDF (216/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
JSR, Jump to subroutine
DIRECT
Main program
PC
$9D = JSR
dd
RTN Next instruction
IND, X
Main program
PC
$AD = JSR
ff
RTN Next instruction
IND, Y
Main program
PC
$18 = PRE
$AD = JSR
ff
RTN Next instruction
EXTEND
Main program
PC
$BD = JSR
hh
ll
RTN Next instruction
RTS, Return from subroutine
Main program
PC
$39 = RTS
SP–2
SP–1
SP
Stack
RTN_H
RTN_L
SP
SP+1
SP+2
Stack
RTN_H
RTN_L
BSR, Branch to subroutine
Main program
PC
$8D = BSR
rr
RTN Next instruction
SP–2
SP–1
SP
Stack
RTN_H
RTN_L
SWI, Software interrupt
Main program
PC
$3F = SWI
RTN
WAI, Wait for interrupt
Main program
PC
$3E = WAI
RTN
SP–9
SP–8
SP–7
SP–6
SP–5
SP–4
SP–3
SP–2
SP–1
SP
Stack
Condition Code
Accumulator B
Accumulator A
Index register (IX_H)
Index register (IX_L)
Index register (IY_H)
Index register (IY_L)
RTN_H
RTN_L
RTI, Return from interrupt
Interrupt program
PC
$3B = RTI
SP
SP+1
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9
Stack
Condition Code
Accumulator B
Accumulator A
Index register (IX_H)
Index register (IX_L)
Index register (IY_H)
Index register (IY_L)
RTN_H
RTN_L
Legend
RTN Address of the next instruction in the main program, to be executed on return from subroutine
RTN_H More significant byte of return address
RTN_L Less significant byte of return address
Shaded cells show stack pointer position after the operation is complete
dd 8-bit direct address ($0000–$00FF); the high byte is assumed to be $00
ff 8-bit positive offset ($00 to $FF (0 to 256)) is added to the index register contents
hh High order byte of 16-bit extended address
ll Low order byte of 16-bit extended address
rr Signed relative offset ($80 to $7F (–128 to +127)); offset is relative to the address following the offset byte
Technical Data
CPU Core and Instruction Set
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MC68HC11P2 — Rev 1.0