MC68HC11P2 Datasheet, PDF (189/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
10.3.6 OPTION — System configuration options register 1
System config. options 1
(OPTION)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0039 ADPU CSEL IRQE DLY CME FCME CR1 CR0 0001 0000
The special-purpose OPTION register sets internal system configuration
options during initialization. The time protected control bits (IRQE, DLY,
FCME and CR[1:0]) can be written to only once in the first 64 cycles after
a reset and then they become read-only bits. This minimizes the
possibility of any accidental changes to the system configuration. They
may be written at any time in special modes.
ADPU — A/D power-up (Refer to Analog-to-Digital Converter)
1 = A/D system power enabled.
0 = A/D system disabled, to reduce supply current.
CSEL — Clock select (Refer to Analog-to-Digital Converter)
1 = A/D and EEPROM use internal RC clock source (about
1.5 MHz).
0 = A/D and EEPROM use system E clock (must be at least 1MHz).
IRQE — Configure IRQ for falling edge sensitive operation (Refer to
Operating Modes and On-Chip Memory)
1 = Falling edge sensitive operation.
0 = Low level sensitive operation.
DLY — Enable oscillator start-up delay (Refer to Operating Modes and
On-Chip Memory)
1 = A delay of approximately 4000 E clock cycles is imposed as the
MCU is started up from the STOP mode.
0 = The oscillator start-up delay coming out of STOP is bypassed.
CME — Clock monitor enable
1 = Clock monitor enabled.
0 = Clock monitor disabled.
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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Technical Data