MC68HC11P2 Datasheet, PDF (204/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
affected significantly by the WAIT condition. However, the A/D converter
current can be eliminated by writing the ADPU bit to zero. The SPI
system is enabled or disabled by the SPE control bit. The SCI transmitter
is enabled or disabled by the TE bit, and the SCI receiver is enabled or
disabled by the RE bit. Therefore the power consumption in WAIT is
dependent on the particular application.
10.7.2 STOP
Executing the STOP instruction while the S-bit in the CCR is equal to
zero places the MCU in the STOP condition. If the S-bit is not zero, the
STOP opcode is treated as a no-op (NOP). The STOP condition offers
minimum power consumption because all clocks, including the crystal
oscillator, are stopped while in this mode. To exit STOP and resume
normal processing, a logic low level must be applied to one of the
external interrupts (IRQ or XIRQ) or to the RESET pin. A pending edge-
triggered IRQ can also bring the CPU out of STOP.
Because all clocks are stopped in this mode, all internal peripheral
functions also stop. The data in the internal RAM is retained as long as
V_DD power is maintained. The CPU state and I/O pin levels are static and
are unchanged by STOP. Therefore, when an interrupt comes to restart
the system, the MCU resumes processing as if there were no
interruption. If reset is used to restart the system a normal reset
sequence results where all I/O pins and functions are also restored to
their initial states.
To use the IRQ pin as a means of recovering from STOP, the I-bit in the
CCR must be clear (IRQ not masked). The XIRQ pin can be used to
wake up the MCU from STOP regardless of the state of the X-bit in the
CCR, although the recovery sequence depends on the state of the X-bit.
If X is set to zero (XIRQ not masked), the MCU starts up, beginning with
the stacking sequence leading to normal service of the XIRQ request. If
X is set to one (XIRQ masked or inhibited), then processing continues
with the instruction that immediately follows the STOP instruction, and
no XIRQ interrupt service is requested or pending.
Technical Data
Resets and Interrupts
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MC68HC11P2 — Rev 1.0