MC68HC11P2 Datasheet, PDF (27/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Pin Descriptions
Phase-locked loop (XFC, VDDSYN)
The PLL filter has two bandwidths that are automatically selected by the
PLL, if the AUTO bit in PLLCR is set. Whenever the PLL is first enabled,
the wide bandwidth mode is used. This enables the PLL frequency to
ramp up quickly. When the output frequency is near the desired value,
the filter is switched to the narrow bandwidth mode, to make the final
frequency more stable. Manual control is possible, by clearing AUTO in
PLLCR, and setting the appropriate value for BWC.
A block diagram of the PLL circuitry is given in Figure 2-4.
t_REF
Phase
detect
EXTAL
Low frequency
crystal oscillator
PCOMP
V_DDSYN
XFC
Loop filter
VCO
EXTAL
Bus clock
select
BCS
4XCLK
To clock
generation
circuitry
t_FB
Frequency divider
VCOOUT
Module clock
select
ST4XCK
For SCI
and timer
EXTAL
SYNR
MCS
Figure 2-4. PLL circuit
2.7.1 Synchronization of PLL with subsystems
The timer and SCI subsystems operate off the EXTAL clock, but are
accessed by the CPU relative to the internal PH2 signal. Although the
EXTAL clock is used as the reference for the PLL, the PH2 clock and the
module clocks for the timer and the SCI are not synchronized. In order
MC68HC11P2 — Rev 1.0
Pin Descriptions
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Technical Data