MC68HC11P2 Datasheet, PDF (48/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Table 3-2. Register and control bit assignments (Sheet 2 of 4)
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer output compare 4 (TOC4) high $001C (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) 1111 1111
Timer output compare 4 (TOC4) low $001D (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
Capture 4/compare 5 (TI4/O5) high $001E (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) 1111 1111
Capture 4/compare 5 (TI4/O5) low $001F (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
Timer control 1 (TCTL1)
$0020 OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5 0000 0000
Timer control 2 (TCTL2)
$0021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000
Timer interrupt mask 1 (TMSK1) $0022 OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I 0000 0000
Timer interrupt flag 1 (TFLG1) $0023 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F 0000 0000
Timer interrupt mask 2 (TMSK2) $0024 TOI RTII PAOVI PAII 0
0 PR1 PR0 0000 0000
Timer interrupt flag 2 (TFLG2) $0025 TOF RTIF PAOVF PAIF 0
0
0
0 0000 0000
Pulse accumulator control (PACTL) $0026 0 PAEN PAMOD PEDGE 0 I4/O5 RTR1 RTR0 0000 0000
Pulse accumulator count (PACNT) $0027 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undefined
SPI control (SPCR)
$0028 SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu
SPI status (SPSR)
$0029 SPIF WCOL 0 MODF 0
0
0
0 0000 0000
SPI data (SPDR)
$002A (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undefined
EPROM programming (EPROG) ^{‡ $002B MBE 0 ELAT EXCOL EXROW 0}
0 EPGM 0000 0000
Port pull-up assignment (PPAR) $002C 0
0
0
0 HPPUE GPPUE FPPUE BPPUE 0000 1111
reserved
$002D
PLL control (PLLCR)
$002E PLLON BCS AUTO BWC VCOT MCS LCK WEN 1010 1000
Synthesizer program (SYNR)
$002F SYNX1 SYNX0 SYNY5 SYNY4 SYNY3 SYNY2 SYNY1 SYNY0 0000 1011
A/D control & status (ADCTL)
$0030 CCF
0 SCAN MULT CD CC CB CA u0uu uuuu
A/D result 1 (ADR1)
$0031 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undefined
A/D result 2 (ADR2)
$0032 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undefined
A/D result 3 (ADR3)
$0033 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undefined
A/D result 4 (ADR4)
$0034 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undefined
Block protect (BPROT)
$0035 BULKP 0 BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1011 1111
reserved
$0036
EEPROM mapping (INIT2)
$0037 EE3 EE2 EE1 EE0 M3DL1 M3DL0 M2DL1 M2DL0 0000 0000
System config. options 2 (OPT2) $0038 LIRDV CWOM STRCH IRVNE LSBF SPR2 0
0 000x 0000
System config. options 1 (OPTION) $0039 ADPU CSEL IRQE DLY CME FCME CR1 CR0 0001 0000
COP timer arm/reset (COPRST) $003A (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undefined
EEPROM programming (PPROG) $003B ODD EVEN 0 BYTE ROW ERASE EELAT EEPGM 0000 0000
Highest priority interrupt (HPRIO) $003C RBOOT SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
RAM & I/O mapping (INIT)
$003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000
Technical Data
Operating Modes and On-Chip Memory
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MC68HC11P2 — Rev 1.0