MC68HC11P2 Datasheet, PDF (218/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
11.3.6 Condition code register (CCR)
This 8-bit register contains five condition code indicators (C, V, Z, N, and
H), two interrupt masking bits, (IRQ and XIRQ) and a stop disable bit (S).
In the M68HC11 CPU, condition codes are automatically updated by
most instructions. For example, load accumulator A (LDAA) and store
accumulator A (STAA) instructions automatically set or clear the N, Z,
and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y
(ABY), and transfer/exchange instructions do not affect the condition
codes. Refer to Table 11-2, which shows the condition codes that are
affected by a particular instruction.
11.3.6.1 Carry/borrow (C)
The C-bit is set if the arithmetic logic unit (ALU) performs a carry or
borrow during an arithmetic operation. The C-bit also acts as an error
flag for multiply and divide operations. Shift and rotate instructions
operate with and through the carry bit to facilitate multiple-word shift
operations.
11.3.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow.
Otherwise, the V-bit is cleared.
11.3.6.3 Zero (Z)
The Z-bit is set if the result of an arithmetic, logic, or data manipulation
operation is zero. Otherwise, the Z-bit is cleared. Compare instructions
do an internal implied subtraction and the condition codes, including Z,
reflect the results of that subtraction. A few operations (INX, DEX, INY,
and DEY) affect the Z-bit and no other condition flags. For these
operations, only ‘=’ and ‘¦’ conditions can be determined.
11.3.6.4 Negative (N)
The N-bit is set if the result of an arithmetic, logic, or data manipulation
Technical Data
CPU Core and Instruction Set
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MC68HC11P2 — Rev 1.0