MC68HC11P2 Datasheet, PDF (214/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
CPU Core and Instruction Set
11.3 Registers
M68HC11 CPU registers are an integral part of the CPU and are not
addressed as if they were memory locations. The seven registers are
shown in Figure 11-1 and are discussed in the following paragraphs.
7 Accumulator A 0 7 Accumulator B 0
15
Double accumulator D
0
15
Index register X
0
15
Index register Y
0
15
Stack pointer
0
15
Program counter
0
Condition code register
SXH I NZVC
A:B
D
IX
IY
SP
PC
CCR
Carry
Overflow
Zero
Negative
I interrupt mask
Half carry (from bit 3)
X interrupt mask
Stop disable
Figure 11-1. Programming model
11.3.1 Accumulators A, B and D
Accumulators A and B are general-purpose 8-bit registers that hold
operands and results of arithmetic calculations or data manipulations.
For some instructions, these two accumulators are treated as a single
double-byte (16-bit) accumulator called accumulator D. Although most
operations can use accumulators A or B interchangeably, the following
exceptions apply:
• The ABX and ABY instructions add the contents of 8-bit
accumulator B to the contents of 16-bit register X or Y, but there
are no equivalent instructions that use A instead of B.
• The TAP and TPA instructions transfer data from accumulator A
to the condition code register, or from the condition code register
Technical Data
CPU Core and Instruction Set
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MC68HC11P2 — Rev 1.0