MC68HC11P2 Datasheet, PDF (76/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Parallel Input/Output
The state of the pins on reset is mode dependent. In single chip or
bootstrap mode, port B pins are high-impedance inputs with selectable
internal pull-up resistors (see Internal pull-up/pull-down resistors). In
expanded or test mode, port B pins are high order address outputs and
PORTB/DDRB are not in the memory map.
4.4.1 PORTB — Port B data register
Port B data (PORTB)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0004 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 undefined
The bits may be read and written at any time and are not affected by
reset.
4.4.2 DDRB — Data direction register for port B
Data direction B (DDRB)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0002 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 0000 0000
DDB[7:0] — Data direction for port B
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
Technical Data
Parallel Input/Output
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MC68HC11P2 — Rev 1.0