MC68HC11P2 Datasheet, PDF (156/268 Pages) Motorola, Inc – Microcontrollers

Timing System
Freescale Semiconductor, Inc.
8.6.2 TFLG2 — Timer interrupt flag register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer interrupt flag 2 (TFLG2) $0025 TOF RTIF PAOVF PAIF 0
0
0
0 0000 0000
Bits of this register indicate the occurrence of timer system events.
Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow
the timer subsystem to operate in either a polled or interrupt driven
system. Clear flags by writing a one to the corresponding bit position(s).
NOTE: Bits in TFLG2 correspond bit for bit with flag bits in TMSK2. Ones in
TMSK2 enable the corresponding interrupt sources.
TOF — Timer overflow interrupt flag
1 = The timer has overflowed, from $FFFF to $0000.
0 = No timer overflow has occurred.
RTIF — Real-time interrupt flag
1 = RTI period has elapsed.
0 = RTI flag has been cleared.
The RTIF status bit is automatically set to one at the end of every RTI
period.
PAOVF — Pulse accumulator overflow interrupt flag (refer to Pulse
accumulator)
PAIF — Pulse accumulator input edge interrupt flag (refer to Pulse
accumulator)
Bits [3:0] — Not implemented; always read zero
Technical Data
Timing System
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MC68HC11P2 — Rev 1.0