MC68HC11P2 Datasheet, PDF (147/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timing System
Output compare
8.5.1 TOC1–TOC4 — Timer output compare registers
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer output compare 1 (TOC1)
high
$0016 (bit 15)
(14)
(13)
(12)
(11)
(10)
(9) (bit 8) 1111 1111
Timer output compare 1 (TOC1)
low
$0017
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1) (bit 0) 1111 1111
Timer output compare 2 (TOC2)
high
$0018 (bit 15)
(14)
(13)
(12)
(11)
(10)
(9) (bit 8) 1111 1111
Timer output compare 2 (TOC2)
low
$0019
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1) (bit 0) 1111 1111
Timer output compare 3 (TOC3)
high
$001A (bit 15)
(14)
(13)
(12)
(11)
(10)
(9) (bit 8) 1111 1111
Timer output compare 3 (TOC3)
low
$001B
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1) (bit 0) 1111 1111
Timer output compare 4 (TOC4)
high
$001C (bit 15)
(14)
(13)
(12)
(11)
(10)
(9) (bit 8) 1111 1111
Timer output compare 4 (TOC4)
low
$001D
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1) (bit 0) 1111 1111
All output compare registers are 16-bit read-write. Each is initialized to
$FFFF at reset. If an output compare register is not used for an output
compare function, it can be used as a storage location. A write to the
high-order byte of an output compare register pair inhibits the output
compare function for one bus cycle. This inhibition prevents
inappropriate subsequent comparisons. Coherency requires a complete
16-bit read or write. However, if coherency is not needed, byte accesses
can be used.
For output compare functions, write a comparison value to output
compare registers TOC1–TOC4 and TI4/O5. When TCNT value
matches the comparison value, specified pin actions occur.
All TOCx register pairs reset to ones ($FFFF).
MC68HC11P2 — Rev 1.0
Timing System
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Technical Data