MC68HC11P2 Datasheet, PDF (26/268 Pages) Motorola, Inc – Microcontrollers

Pin Descriptions
Freescale Semiconductor, Inc.
2.6 E clock output (E)
E is the output connection for the internally generated E clock. The signal
from E is used as a timing reference. The frequency of the E clock output
is one quarter that of the input frequency at the XTAL and EXTAL pins
(except when the PLL is used as the clock source). When E clock output
is low, an internal process is taking place; when it is high, data is being
accessed. All clocks, including the E clock, are halted when the MCU is
in STOP mode. The E clock output can be turned off in single chip
modes to reduce the effects of RFI.
2.7 Phase-locked loop (XFC, VDDSYN)
The XFC and VDDSYN pins are the inputs for the on-chip PLL (phase-
locked loop) circuitry. On reset all the device clocks are derived from the
EXTAL input. The EXTAL clock is used as a reference for the PLL circuit,
which generates a clock that is a multiple of the EXTAL frequency. Once
the PLL has stabilized, alternate clocks may be selected.
VDDSYN is the power supply pin for the PLL. Connecting it high enables
the internal low frequency oscillator circuitry designed for the PLL. The
PLL has been designed particularly for use with 614.4 and 640kHz
crystals, though other values may be used. The maximum
recommended crystal frequency for PLL operation is 2MHz. Above this
frequency VDDSYN should be grounded to disable the PLL and enable
the high frequency oscillator circuit; in this state EXTAL is designed for
16MHz operation and XFC may be left unconnected.
The PLL consists of a variable bandwidth loop filter, a voltage controlled
oscillator (VCO), a feedback frequency divider and a digital phase
detector. VDDSYN is the supply voltage for the PLL and must be suitably
bypassed. The external capacitor on XFC should be located as close to
the chip as possible to minimize noise. A typical value for this capacitor
is 0.047µF, for a crystal frequency of 614.4kHz.⁽¹⁾
1. In general, a larger capacitor will improve the PLL’s frequency stability, at the expense of in-
creasing the time required for it to settle (t ) at the desired frequency. For a 32kHz appli-
Technical Data
Pin Descriptions
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MC68HC11P2 — Rev 1.0