MC68HC11P2 Datasheet, PDF (144/268 Pages) Motorola, Inc – Microcontrollers

Timing System
Freescale Semiconductor, Inc.
8.4.2 TIC1–TIC3 — Timer input capture registers
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer input capture 1 (TIC1) high $0010 (bit 15) (14) (13) (12) (11) (10)
(9)
(bit 8)
not
affected
Timer input capture 1 (TIC1) low $0011 (bit 7) (6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
not
affected
Timer input capture 2 (TIC2) high $0012 (bit 15) (14) (13) (12) (11) (10)
(9)
(bit 8)
not
affected
Timer input capture 2 (TIC2) low $0013 (bit 7) (6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
not
affected
Timer input capture 3 (TIC3) high $0014 (bit 15) (14) (13) (12) (11) (10)
(9)
(bit 8)
not
affected
Timer input capture 3 (TIC3) low $0015 (bit 7) (6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
not
affected
When an edge has been detected and synchronized, the 16-bit free-
running counter value is transferred into the input capture register pair
as a single 16-bit parallel transfer. Timer counter value captures and
timer counter incrementing occur on opposite half-cycles of the phase 2
clock so that the count value is stable whenever a capture occurs. Input
capture values can be read from a pair of 8-bit read-only registers. A
read of the high-order byte of an input capture register pair inhibits a new
capture transfer for one bus cycle. If a double-byte read instruction, such
as LDD, is used to read the captured value, coherency is assured. When
a new input capture occurs immediately after a high-order byte read,
transfer is delayed for an additional cycle but the value is not lost.
The TICx registers are not affected by reset.
Technical Data
Timing System
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MC68HC11P2 — Rev 1.0