MC68HC11P2 Datasheet, PDF (139/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timing System
Timer structure
Table 8-1. Timer resolution and capacity
Clock
4.0MHz 8.0MHz 12.0MHz 16.0MHz
Control bits ^{1.0MHz 2.0MHz 3.0MHz 4.0MHz}
PR[1:0] 1000ns 500ns 333ns 250ns
00
1.0µs 500ns 333ns 250ns
65.536ms 32.768ms 21.845ms 16.384ms
01
4.0 µs
2.0µs 1.333µs 1.0µs
262.14ms 131.07ms 87.381ms 65.536ms
10
8.0 µs
4.0µs 2.667µs 2.0µs
524.29ms 262.14ms 174.76ms 131.07ms
11
16.0µs 8.0µs 5.333µs 4.0µs
1049 ms 524.29ms 349.53ms 262.14ms
4E
E
1/E
1/E
2¹⁶/E
4/E
2¹⁸/E
8/E
2¹⁹/E
16/E
2²⁰/E
XTAL
E clock
Period
– resolution
– overflow
– resolution
– overflow
– resolution
– overflow
– resolution
– overflow
8.3 Timer structure
The timer functions share I/O with all eight pins of port A:
Pin
Alternate function
PA0
IC3
PA1
IC2
PA2
IC1
PA3 OC5 and/or OC1, or IC4
PA4
OC4 and/or OC1
PA5
OC3 and/or OC1
PA6
OC2 and/or OC1
PA7
PAI and/or OC1
Figure 8-2 shows the capture/compare system block diagram. The port
A pin control block includes logic for timer functions and for general-
purpose I/O. For pins PA3, PA2, PA1 and PA0, this block contains both
the edge-detection logic and the control logic that enables the selection
of which edge triggers an input capture. The digital level on PA[3:0] can
be read at any time (read PORTA register), even if the pin is being used
MC68HC11P2 — Rev 1.0
Timing System
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Technical Data