MC68HC11P2 Datasheet, PDF (85/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Parallel Input/Output
System configuration
CWOM — Port C wired-OR mode
1 = Port C outputs are open-drain.
0 = Port C operates normally.
STRCH — Stretch external accesses (refer to Operating Modes and
On-Chip Memory)
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
IRVNE — Internal read visibility/not E (refer to Operating Modes and
On-Chip Memory)
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives
out from the chip.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
LSBF — LSB first enable (refer to Serial Peripheral Interface (SPI))
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
SPR2 — SPI clock rate select (refer to Serial Peripheral Interface
(SPI))
Bits 1, 0 — not implemented; always read zero.
4.12.2 CONFIG — System configuration register
Address bit 7 bit 6
Configuration control (CONFIG) $003F ROMAD 1
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
1 PARENNOSECNOCOPROMON EEON x11x 1xxx
ROMAD — ROM mapping control (refer to Operating Modes and On-
Chip Memory)
1 = ROM addressed from $8000 to $FFFF.
0 = ROM addressed from $0000 to $7FFF (expanded mode only).
MC68HC11P2 — Rev 1.0
Parallel Input/Output
For More Information On This Product,
Go to: www.freescale.com
Technical Data