MC68HC11P2 Datasheet, PDF (18/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
General Description
1.3 Features
• Low power, high performance M68HC11 CPU core, with 4MHz
bus capability
• Power saving PLL clock circuit, with automatic disable during
WAIT mode
• 32kbytes of User ROM (MC68HC11P2); 32kbytes User EPROM
(MC68HC711P2)
• 1kbyte of RAM
• 640 bytes of byte-erasable User EEPROM, with on-chip charge
pump
• Up to 50 general purpose I/O lines, plus up to 12 input-only lines
• Non-multiplexed address and data buses, permitting direct access
to the full 64k address map
• 16-bit timer with 3/4 input captures and 4/5 output compares;
pulse accumulator and COP watchdog timer
• Three 8- or 9-bit SCI subsystems, two with MI BUS^† capability
• SPI subsystem, with software selectable MSB/LSB first option
• 8-channel, 8-bit analog-to-digital (A/D) converter
• Four 8-bit PWM timer channels (may be concatenated to form
one, or two, 16-bit channels)
• Available in 84-pin PLCC or 84-pin CERQUAD packages
Technical Data
General Description
For More Information On This Product,
Go to: www.freescale.com
MC68HC11P2 — Rev 1.0