MC68HC11P2 Datasheet, PDF (199/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
Reset and interrupt priority
Table 10-4. Interrupt and reset vector assignments
Vector address
Interrupt source
CCR Local
mask bit mask
FFC0, C1 – FFD0, D1 reserved
—
—
FFD2, D3
• SCI/MI BUS3 receive data register full
• SCI/MI BUS3 receiver overrun
• SCI3 transmit data register empty
I
• SCI3 transmit complete
• SCI3 idle line detect
RIE3
RIE3
TIE3
TCIE3
ILIE3
FFD4, D5
• SCI/MI BUS2 receive data register full
• SCI/MI BUS2 receiver overrun
• SCI2 transmit data register empty
I
• SCI2 transmit complete
• SCI2 idle line detect
RIE2
RIE2
TIE2
TCIE2
ILIE2
FFD6, D7
• SCI1 receive data register full
• SCI1 receiver overrun
• SCI1 transmit data register empty
RIE
RIE
I
TIE
• SCI1 transmit complete
• SCI1 idle line detect
TCIE
ILIE
FFD8, D9
SPI serial transfer complete
I
SPIE
FFDA, DB
Pulse accumulator input edge
I
PAII
FFDC, DD
Pulse accumulator overflow
I
PAOVI
FFDE, DF
Timer overflow
I
TOI
FFE0, E1
Timer input capture 4/output compare 5
I
I4/O5I
FFE2, E3
Timer output compare 4
I
OC4I
FFE4, E5
Timer output compare 3
I
OC3I
FFE6, E7
Timer output compare 2
I
OC2I
FFE8, E9
Timer output compare 1
I
OC1I
FFEA, EB
Timer input capture 3
I
IC3I
FFEC, ED
Timer input capture 2
I
IC2I
FFEE, EF
Timer input capture 1
I
IC1I
FFF0, F1
Real-time interrupt
I
RTII
FFF2, F3
IRQ pin
I
None
FFF4, F5
XIRQ pin
X
None
FFF6, F7
Software interrupt
None None
FFF8, F9
Illegal opcode trap
None None
FFFA, FB
COP failure
None NOCOP
FFFC, FD
Clock monitor fail
None CME
FFFE, FF
RESET
None None
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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Technical Data