MC68HC11P2 Datasheet, PDF (245/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Electrical Specifications
Control timing
12.7.4 Nonmultiplexed expansion bus timing
(V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H)
Num
Characteristic ⁽¹⁾
2.0 MHz
3.0 MHz
Symbol
Min. Max. Min. Max.
Frequency of operation (E clock frequency) f_OP
0 2.0 0 3.0
1 E clock period
t_CYC 500 — 333 —
2 _{Pulse width, E low} ^{(2), (3)}
PW_EL 230 — 147 —
3 _{Pulse width, E high} ^{(2), (3)}
PW_EH 225 — 142 —
4A E clockrise time
4B fall time
t_r
— 20 — 20
t_f
— 20 — 18
9 _{Address hold time} ⁽³⁾
t_AH
53 — 32 —
11 _{Address delay time} ⁽³⁾
t_AD
— 103 — 82
12 _{Address valid to E rise time} ⁽³⁾
t_AV
127 —
65
—
17 Read data set-up time
t_DSR
30
—
30
—
18 Read data hold time
t_DHR
0
—
0
—
19 Write data delay time
t_DDW
—
40
—
40
21 _{Write data hold time} ⁽³⁾
t_DHW
63
—
42
—
29 _{MPU address access time} ⁽³⁾
t_ACCA 347 — 203 —
39 _{Write data set-up time} ⁽³⁾
t_DSW 185 — 102 —
57 Address valid to data tristate time
t_AVDZ
—
10
—
10
1. All timing is given with respect to 20% and 70% of V_DD, unless otherwise noted.
2. Input clock duty cycles other than 50% will affect the bus performance.
3. For f_OP 2MHz the following formulae may be used to calculate parameter values:
PW_EL = t_CYC/2 – 20ns PW_EH = t_CYC/2 – 25ns
t_AH = t_CYC/8 – 10ns t_AD = t_CYC/8 + 40ns
t_AV = PW_EL – t_AD t_DHW = t_CYC/8
t_ACCA = t_CYC – t_f – t_DSR – t_ADt_DSW = PW_EH – t_DDW
t_ECSA = PW_EH – t_ECSD – t_DSRt_ACSD = t_CYC/4 + 40ns
t_ACSA = t_CYC – t_f – t_DSR – t_ACSD
4.0 MHz
Min. Max.
0 4.0
Unit
MHz
250 — ns
105 — ns
100 — ns
—
—
20
15
ns
21 — ns
— 71 ns
34 — ns
20 — ns
0
— ns
— 40 ns
31 — ns
144 — ns
60 — ns
— 10 ns
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Technical Data