MC68HC11P2 Datasheet, PDF (167/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timing System
Pulse-width modulation (PWM) timer
Table 8-4. Clock A and clock B prescalers
PCKA[2:1]
00
01
10
11
Clock A
E
E/2
E/4
E/8
PCKB[3:1]
000
001
010
011
100
101
110
111
Clock B
E
E/2
E/4
E/8
E/16
E/32
E/64
E/128
8.9.3 PWPOL — PWM timer polarity & clock source select register
Pulse width polarity select
(PWPOL)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000
PCLK[4:3] — Pulse width channel 4/3 clock select
1 = Clock S is source.
0 = Clock B is source.
PCLK[2:1] — Pulse width channel 2/1 clock select
1 = Clock S is source.
0 = Clock A is source.
PPOL[4:1] — Pulse width channel x polarity
1 = PWM channel x output is high at the beginning of the clock
cycle and goes low when duty count is reached.
0 = PWM channel x output is low at the beginning of the clock cycle
and goes high when duty count is reached.
Each channel has a polarity bit that allows a cycle to start with either
a high or a low level. This is shown on the block diagram, Figure 8-4,
as a selection of either the Q output or the Q output of the PWM output
flip flop. When one of the bits in the PWPOL register is set, the
associated PWM channel output is high at the beginning of the clock
cycle, then goes low when the duty count is reached.
MC68HC11P2 — Rev 1.0
Timing System
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Technical Data