MC68HC11P2 Datasheet, PDF (202/268 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
10.6.3 Illegal opcode trap
Because not all possible opcodes or opcode sequences are defined, the
MCU includes an illegal opcode detection circuit, which generates an
interrupt request. When an illegal opcode is detected and the interrupt is
recognized, the current value of the program counter is stacked. After
interrupt service is complete, the user should reinitialize the stack pointer
to ensure that repeated execution of illegal opcodes does not cause
stack underflow. Left uninitialized, the illegal opcode vector can point to
a memory location that contains an illegal opcode. This condition causes
an infinite loop that causes stack underflow. The stack grows until the
system crashes.
The illegal opcode trap mechanism works for all unimplemented
opcodes on all four opcode map pages. The address stacked as the
return address for the illegal opcode interrupt is the address of the first
byte of the illegal opcode. Otherwise, it would be almost impossible to
determine whether the illegal opcode had been one or two bytes. The
stacked return address can be used as a pointer to the illegal opcode, so
that the illegal opcode service routine can evaluate the offending
opcode.
10.6.4 Software interrupt
SWI is an instruction, and thus cannot be interrupted until complete. SWI
is not inhibited by the global mask bits in the CCR. Because execution
of SWI sets the I mask bit, once an SWI interrupt begins, other interrupts
are inhibited until SWI is complete, or until user software clears the I bit
in the CCR.
10.6.5 Maskable interrupts
The maskable interrupt structure of the MCU can be extended to include
additional external interrupt sources through the IRQ pin. The default
configuration of this pin is a low-level sensitive wired-OR network. When
an event triggers an interrupt, a software accessible interrupt flag is set.
Technical Data
Resets and Interrupts
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MC68HC11P2 — Rev 1.0